For example, in double diffused silicon planar transistors having an emitter produced by phosphorus diffusion, in the base zone beneath the emitter there occurs the so-called emitter-dip effect which impedes a check on base width and current amplification and which increases the inner base bulk resistance. In addition, the emitter efficiency is well below the expected theoretical value based on the doping. When arsenic is used for the emitter doping, although generally no emitter-dip effect occurs, here too the theoretical values of the emitter efficiency are nowhere near reached.
Both effects have their origin in the conventionally high surface concentration in the emitter due to the production of crystal faults on the one hand and increased recombination of the minority carriers and reduction in the effective emitter doping due to the reduction in the band spacing on the other hand.
The so-called polysil emitter has already become known as a possible way to avoid these disadvantages. The technology which forms the basis of this principle consists in screening the silicon monocrystal from the harmfully high concentration in the production of the emitter. To this end, on the completion of the conventional planar processes, including the base diffusion, the emitter window is opened in the surface oxide and then a thin layer of polycrystalline, undoped silicon is deposited by conventional processes. Then, for example, phosphorus is diffused into the monocrystal through the polycrystalline silicon layer. A disturbingly high doping concentration then occurs on the surface of the polycrystalline silicon layer, and it is possible to set the concentration of the doping in the monocrystal in accordance with the diffusion time.
Transistors produced in this way exhibit no emitter-dip effect with high current amplification. The penetration depth is extremely small, and the layer resistance of the base beneath the emitter is only slightly increased. However, with this polysil technology, a strong influence of the polysilicon deposition parameters and the boundary properties between polysil layer and monocrystal on the electrical transistor data can be observed.
The aim of the present invention is to avoid the disadvantages resulting from the above mentioned conditions, while simultaneously improving the transistor properties.